Article ID: 000077965 Content Type: Troubleshooting Last Reviewed: 09/02/2012

Can I have more than one DDR3 SDRAM (with leveling) memory interface located in a single IO sub-bank for Stratix IV device family?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For UniPHY based DDR3 SDRAM (with leveling) memory interface if two DDR3 SDRAM interfaces are sharing PLL, you can have more than one DDR3 SDRAM interfaces in one sub-bank.

You can not have more than one Altmemphy based DDR3 SDRAM (with leveling) memory interface located in a single IO sub-bank for Stratix® III and Stratix IV device family.

Stratix III and Stratix IV devices have only one leveling delay chain per I/O sub-bank.  You can only have one memory interface in each I/O sub-bank (such as I/O sub-banks 1A, 1B, and 1C) when you use leveling delay chains if you are not sharing the PLL since two different clocks can not feed one leveling delay chain. Sharing of PLLs is only available in UniPHY based DDR3 SDRAM interfaces.

Related Products

This article applies to 3 products

Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA