If you constrain the RLDRAM II design using DDR Timing Wizard (DTW) in Quartus® II software version 8.1, you will see recovery/removal timing violations. However, these are false paths that are not correctly constrained. To set the false path assignments, add the following lines to the bottom of the DTW-generated SDC file and rerun TimeQuest Timing Analyzer.
set_false_path -from [get_clocks {dtw_read_<memory_clock_name>*}] -to [get_clocks {g_stratixii_pll_rldramii_pll_inst|altpll_component|pll|clk[0]}]
set_false_path -from [get_clocks {g_stratixii_pll_rldramii_pll_inst|altpll_component|pll|clk[0]}] -to [get_clocks {dtw_read__<memory_clock_name>*}]