Article ID: 000077639 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Reconfiguration Ports Not Available for Arria V and Cyclone V Hard IP for PCI Express IP Cores

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Arria V Hard IP for PCI Express User Guide and Cyclone V Hard IP for PCI Express User Guide show large busses for the reconfig_to_xcvr and reconfig_from_xcvr interfaces. However, each of these interfaces only includes one signal in the Quartus II 11.1 and 11.1 SP1 releases. The reconfig_to_xcvr interface of the conduit type in Qsys only includes the fixedclk_lock output signal. The reconfig_from_xcvr interface of the conduit type in Qsys only includes the busy_xcvr_reconfig input signal.

    Resolution

    No workaround is required. The top-level variants generated by Qsys and the MegaWizard are correct for the Quartus II 11.1 and 11.1 SP1 releases. Version 12.0 of the user guides has been updated to show the correct number of buses and bus widths with reconfiguration support enabled.

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs