Article ID: 000077518 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there any issue with selecting the option “Enable Avalon-MM byte-enable signal” when generating RLDRAMII Controller with UniPHY?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, the option "Enable Avalon-MM byte-enable signal" in the Controller Settings tab of the RLDRAMII Controller with UniPHY in version 11.0 does not have any effect on the controller. When enabled, no controller port for avl_be is created or used in any way.

 

There is no workaround to implement byte enable. This issue will be fixed in the future version of the IP and Quartus® II software.

Related Products

This article applies to 8 products

Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® V E FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® III FPGAs
Stratix® V GX FPGA
Stratix® IV GX FPGA

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