Article ID: 000077506 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see incorrect read capture in DDR3 High Performance (HP) Controller Megacore IP when I reset the core during user mode operation in Quartus II software and IP version 7.2?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

DDR3 HP controller IP does not support calibration in simulation in version 7.2. The simulation is based on bringing the system up from a known starting condition rather than completing the calibration process. In this mode of simulation the reset causes the phase relationship between the phy_clk and resynch_clk_1x to change after the reset. Quartus® II software and IP version 8.0 fixes this issue by supporting calibration during simulation.
 

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Stratix® III FPGAs