Description
DDR3 HP controller IP does not support calibration in simulation in version 7.2. The simulation is based on bringing the system up from a known starting condition rather than completing the calibration process. In this mode of simulation the reset causes the phase relationship between the phy_clk and resynch_clk_1x to change after the reset. Quartus® II software and IP version 8.0 fixes this issue by supporting calibration during simulation.