Article ID: 000077451 Content Type: Product Information & Documentation Last Reviewed: 02/27/2019

How do I assign non 3.0-V I/O standard for nPERST pins of Intel® Stratix® 10 PCI Express* Hard IP ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In some Intel® Stratix® 10 design, 3V I/O bank will not be used as 3.0V signal input and output. And VCCIO3V will be connected to the power supply which is not 3.0V, but such as 1.8V or 1.2V which could share the same power plane with other banks.

    Under this condition, the dedicated pins nPERST[L,R][0:2] have to be assigned non 3.0-V I/O standard.

    So the fitter error may be encountered when nPERST[L,R][0:2] pins are assigned to non 3.0-V I/O standard without any additional assignments. 

    Resolution

    Add 'set_instance_assignment -name USE_AS_3V_GPIO ON -to <signal>' to your QSF file if you are intentionally trying to use a non 3.0-V standard on this pin.

    For instance:

        set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_rstn_pin_perst -entity pcie_example_design
        set_instance_assignment -name USE_AS_3V_GPIO ON -to pcie_rstn_pin_perst -entity pcie_example_design
     

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 SX SoC FPGA

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