Article ID: 000077281 Content Type: Error Messages Last Reviewed: 08/27/2013

Error: SERDES transmitter must drive one output pin

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You will get this error message if you are using dedicated SERDES with pseudo differential LVDS outputs such as LVDS_E_3R, LVDS_E_1R, and BLVDS. When using pseudo differential output standards, you cannot drive the output pin with the dedicated SERDES macro. You must implement the altlvds function in Logic Element (LE) Mode (soft SERDES).

When the Quartus® II software checks the legality for placement, it gives an error because the dedicated SERDES must have a direct connection to an output pin. When using pseudo differential standards, core logic is inserted between the soft SERDES and the output pin.

Related Products

This article applies to 5 products

Stratix® III FPGAs
Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Arria® II GX FPGA