Article ID: 000077195 Content Type: Troubleshooting Last Reviewed: 01/03/2023

Certain Reference Clock Frequencies Cause the Compilation of the Arria® 10 and Cyclone® 10 GX fPLL IP to Fail

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Compilation of the Arria® 10 and Cyclone® 10 fPLL IP may fail during the Fitter stage under the following circumstances:

    • The IP is in Core or Cascade Source mode and the reference clock frequency is in the range of 49 MHz < Fref < 51.5 MHz.
    • The IP is in Transceiver mode and the reference clock frequency is in the range of 50.0 MHz ≤ Fref < 51.5 MHz.

    This issue affects both the Quartus® Prime Standard Edition software and the Quartus Prime Pro Edition software.

    Resolution

    Select the fPLL IP reference clock frequency that does not fall within the specified ranges.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA