Why does tx_st_ready0 remain de-asserted in my customized PCI Express simulation?

This may be seen if the logic in the auto-generated PCI Express® example chaining design top level test bench file <variation name>_example_chaining_pipen1b.vhd is connected to the wrong clock (internal_core_clk_out).

All logic in <variation_name>_example_chaining_pipen1b.vhd must be connected to pld_clk  as shown in PCIe® core instance and the Altera® example entities.

The pld_clk and internal_core_clk_out are logically the same. However  the pld_clk in simulation is not equivalent to internal_core_clk_out due to delta delays.