Article ID: 000076815 Content Type: Troubleshooting Last Reviewed: 05/09/2023

Why are rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop only a single bit wide when Enable multiple packets per cycle was set when configurating the Intel® Arria® 10 FPGA Avalon® Streaming Interface for PCIe Hard IP in 3.0 x8 mode?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
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    Description

    Due to an issue in the Quartus® II software versions 14.1.1 and earlier, the RTL wrapper file for the 3.0 x8 Intel® Arria® 10 FPGA Hard IP for PCI Express incorrectly maps only a single bit of the lower level two bit wide rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop signals when Enable multiple packets per cycle is set.

    Resolution

    To work around this problem, modify the RTL wrapper file, <variation name>.v or <variation name>.vhd, to export both signal bits.