Article ID: 000076383 Content Type: Error Messages Last Reviewed: 02/10/2023

Internal Error: Sub-system: FPP, File: /quartus/periph/fpp/fpp_design.cpp, Line: 213 Port OPORT_BUFFEROUT already exists on IO_CLUSTER cell 177

Environment

  • Intel® Quartus® Prime Pro Edition
  • eSRAM Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error message when targeting Intel® Stratix® 10 MX devices in Intel® Quartus® Prime Pro Software version 18.0.1 and you have a design that includes two instances of the eSRAM Intel® FPGA IP, and both of the cases share a common reference clock signal.

    Each eSRAM Intel® FPGA IP instance requires a dedicated reference clock due to its physical placement on the device.

    Resolution

    To work around this problem, provide a dedicated reference clock to each eSRAM Intel® IP instance in the design. Please refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines for more information about the eSRAM Intel® IP pin requirements.

    A more meaningful error message is generated starting with the Intel® Quartus® Prime Software version 22.3.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA