Article ID: 000075960 Content Type: Troubleshooting Last Reviewed: 07/04/2012

Center PLL in Arria V Cannot Drive Two Independent PHY Clock Networks

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products.

    A fitter error may occur when the center PLL in Arria V devices is used to drive two independent PHY clock networks. This circumstance can occur when the PLL reference clock inputs for two memory interfaces are constrained such that they both use the center PLL.

    Resolution

    The workaround for this issue is to use the center PLL to drive only a single clock tree.

    This issue will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Arria® V FPGAs and SoC FPGAs