Article ID: 000075926 Content Type: Troubleshooting Last Reviewed: 08/12/2012

Which locations are being used during calibration in ALTMEMPHY with leveling?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The ALTMEMPHY leveling sequencer during calibration writes to the following locations:

-Bank 0, 1, and 3
-Row 1
-All columns

Bank 0 is written to for the block training pattern and clock cycle calibration.

Bank 1 is written to for write deskew (DQ).

Bank 2 is written to for write deskew (DM).

For each bank, only row 1 is accessed. The number of columns accessed can vary, but you should avoid writing to all columns in these banks and row 1.

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA