Article ID: 000075311 Content Type: Troubleshooting Last Reviewed: 10/10/2013

Does the Advanced clock phase control adjustment in the HPS DDR3 work?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks.
    Resolution The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software.

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    This article applies to 5 products

    Cyclone® V SX SoC FPGA
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