Article ID: 000075258 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is Synchronizer Identification assignment for UniPHY based QDRII controller ignored by fitter?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may encounter the following report at the Ignored Assignments section in the Fitter report when you build QDRII controller with UniPHY in your design.

Name: Synchronizer Identification
Ignored Entity: qdrii_ctl_read_datapath
Ignored Value: FORCED_IF_ASYNCHRONOUS
Ignored Source: Compiler or HDL Assignment

This is reported because HDL Assginment was ignored during Synthesis.
You should enable Timing-Driven Synthesis in the Analysis & Synthesis Settings to remove this report.

Related Products

This article applies to 3 products

Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA