Article ID: 000074654 Content Type: Error Messages Last Reviewed: 12/11/2015

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may get this error in the Quartus® Prime software for your Arria® V or Cyclone® V based design if you are driving an fPLL and further user logic from the same reference clock pin.

 

 

Resolution

To avoid this error insert a Clock Control Block (ALTCLKCTRL) Megafunction  between the reference clock pin and both the fPLL and the user logic.

For further information on using this IP, refer to Clock Control Block (ALTCLKCTRL) Megafunction User Guide (PDF)

 

 

 

 

Related Products

This article applies to 11 products

Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V GT FPGA
Arria® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V GZ FPGA