Article ID: 000074170 Content Type: Troubleshooting Last Reviewed: 05/14/2014

Why does the PCI Express Hard IP core not transistion through all the required hot reset LTSSM states in simulation?

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the soft reset controller, when hot reset is applied, the LTSSM does not go through every state expected when initiating hot resets.
    Resolution

    This problem can be fixed with the following soft logic code in the file altpcie_rs_serdes.v near line 526:

             exits_r       <= ((rx_signaldetect == 8\'b00000000) & (dl_ltssm_r == 5\'h14)) | (l2_exit_r == 1\'b0) | (hotrst_exit_r == 1\'b0) | (dlup_exit_r == 1\'b0) | (dl_ltssm_r == 5\'h10) /*| (dl_ltssm_r == 5\'h14)*/ | (recovery_rst == 1\'b1) | (ext_dect_quiet==1\'b1);

    This problem is scheduled to be fixed in a future release of the Quartus® II software.

    Related Products

    This article applies to 4 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA