Article ID: 000074105 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I set the Cyclone III or Cyclone IV E device I/O pins to tri-state the Active Parallel (AP) configuration bus for an external master device to take control of the bus?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For another master to take control of the AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset the Cyclone® III or Cyclone IV E device and de-assert the nCE high to disable the Cyclone III or Cyclone IV E device. This resets the Cyclone III or Cyclone IV E device and causes it to tri-state its AP configuration bus. The other master then takes control of the AP configuration bus.

After the other master device is done, it releases the AP configuration bus, then releases the nCE pin, and finally pulses nCONFIG low to restart the configuration. In the AP configuration scheme, multiple masters share the parallel flash and the bus control is negotiated by the nCE pin.

Related Products

This article applies to 1 products

Cyclone® IV E FPGA