Article ID: 000073990 Content Type: Troubleshooting Last Reviewed: 12/23/2022

Why is the RX Core FIFO full if PMA and PCS bonding mode is enabled in H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • L-Tile H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with Quartus® Prime Pro Edition Software version 17.1, the H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP may output incorrect rx_clkout frequency if the PMA and PCS bonding mode is enabled for non-PCIe mode. The incorrect rx_clkout frequency will cause the RX Core FIFO to become full.

    Resolution

    Use PMA-only bonding for non-PCIe mode. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs