Article ID: 000073870 Content Type: Troubleshooting Last Reviewed: 01/18/2023

Why does the EMIF calibration hang when both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP are placed in the same I/O column?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Both the local_cal_fail signal and the local_cal_success signal may not assert high after EMIF calibration when both an Intel® Arria® 10 EMIF IP and an Intel Arria 10 PHYLite IP with dynamic reconfiguration enabled are placed in the same I/O column.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs