Jump Conditional Code Erratum Overview White Paper for Intel® Processors
Starting with the second-generation Intel® Core™ Processors and Intel® Xeon® E3-1200 Series Processors (formerly codenamed Sandy Bridge) and later processor families, the Intel® microarchitecture introduces a microarchitectural structure called the Decoded ICache (also called the Decoded Streaming Buffer or DSB).
The Decoded ICache caches decoded instructions, called micro-ops (μops), coming out of the legacy decode pipeline. The next time the processor accesses the same code, the Decoded ICache provides the μops directly, speeding up program execution.
In some Intel® Processors, there's an erratum (SKX102) that may occur under complex microarchitectural conditions involving jump instructions that span across 64-byte boundaries (cross cache lines). A microcode update (MCU) can prevent this erratum.
For more information about this erratum including how to get the MCU and a list of processor families/processors number series, view the Mitigations for Jump Conditional Code Erratum White Paper (attached below).
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Mitigations for Jump Conditional Code Erratum White Paper (PDF) 
Size: 362 KB
Date: November 2019
Note: PDF files require Adobe Acrobat Reader*.