Verilog HDL: Counter with Asynchronous Reset

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This example describes an 8-bit counter with asynchronous reset and count enable inputs in Verilog HDL. Synthesis tools detect counter designs in HDL code and infer lpm_counter megafunction.

Figure 1. Counter with Asynchronous Reset Top-Level Diagram

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The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1 lists the ports and gives a description for each.