The Platform Designer (formerly Qsys) is the next-generation system integration tool in the Intel® Quartus® Prime software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed†. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.
Platform Designer in the Pro Edition of the Intel Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Platform Designer system design tool. Our training course, System Design with Platform Designer Pro, explores the differences between the Intel Quartus Prime Standard and Pro Edition software versions of the tools, focusing on Platform Designer support for generic components in the Pro Edition - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.
In the Intel Quartus Prime Pro Edition software v18.0, the Platform Designer supports the new features that greatly help with design portability. You can now:
- Allow coherency signals from Stratix 10 HPS interface to be transported to IP via ACE-Lite support
- Generate hierarchical simulation scripts by referencing simulation information of its subsystems and IP components without traversing system hierarchy
- Use Verilog syntax to connect ports in Platform Designer with wire-level connectivity
- Incorporate IP components that use SystemVerilog interfaces into Platform Designer systems
- Experience significant reduction in IP upgrade regeneration time
- More details on all these features are available in the Platform Designer User Guide
Also, please watch the Platform Designer overview video that walks through the process of using the tool...