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CPLD MAX® V
Stato
Launched
Data di lancio
2010
Litografia
180 nm

Risorse

Elementi logici (LE, Logic Element)
2210
Equivalent Macrocells
1700
Pin-to-pin Delay
7 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

Caratteristiche

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V
I/O Power Banks
4
Maximum Output Enables
271
LVTTL/LVCMOS
Emulated LVDS Outputs
32 bit, 66 MHz PCI Compliant
1
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

Specifiche del package

Opzioni package
F256, F324
Dimensione package
17mm x 17mm, 19mm x 19mm

Informazioni supplementari

URL informazioni aggiuntive