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CPLD MAX® V
Stato
Launched
Data di lancio
2010
Litografia
180 nm

Risorse

Elementi logici (LE, Logic Element)
80
Equivalent Macrocells
64
Pin-to-pin Delay
7.5 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

Caratteristiche

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
I/O Power Banks
2
Maximum Output Enables
54
LVTTL/LVCMOS
Emulated LVDS Outputs
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

Specifiche del package

Opzioni package
M64, M68, E64, T100
Dimensione package
4.5mm, x 4.5mm, 5mm x 5mm, 9mm x 9mm, 16mm x 16mm

Informazioni supplementari

URL informazioni aggiuntive