ARM-Based HPS

The Cyclone V SoC FPGA HPS consists of a dual-core ARM Cortex-A9 MPCore* processor, a rich set of peripherals, and a multiport memory controller shared with logic in the FPGA, giving you the flexibility of programmable logic and the cost savings of hard intellectual property (IP) due to:

• Single- or dual-core processor with up to 925 MHz maximum frequency.
• Hardened embedded peripherals eliminate the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic and reducing power consumption.
• Hardened multiport memory controller, shared by the processor and FPGA logic, supports DDR2, DDR3, and LPDDR2 devices with integrated error correction code (ECC) support for high-reliability and safety-critical applications.

High-Bandwidth Interconnect

High-throughput datapaths between the HPS and FPGA fabric provide interconnect performance not possible in two-chip solutions. This tight integration provides:

• Over 100 Gbps peak bandwidth.
  
• Integrated data coherency.
• Significant system power savings by eliminating the external I/O paths between the processor and the FPGA.

Flexible FPGA Fabric

The FPGA logic fabric lets you differentiate your system by implementing custom IP or off-the-shelf preconfigured IP from Intel or its partners into your designs. This allows you to:

• Adapt quickly to varying or changing interface and protocol standards.
• Add custom hardware in the FPGA to accelerate time-critical algorithms and create a compelling competitive edge.
• Quickly deploy a custom ARM processor without the extensive design, verification, and non-recurring engineering (NRE) costs required in ASICs.

Architecture Matters

Because Cyclone V SoC FPGAs integrate many hard IP blocks, you can lower your overall system cost, power, and design time. SoC FPGAs are more than the sum or their parts. How the processor and FPGA systems work together matters greatly to your system’s performance, reliability, and flexibility. Intel® SoC FPGAs are designed to:

• Preserve the flexibility of processor boot or FPGA configuration sequence, system response to processor reset, and independent memory interfaces of a two-chip solution.
• Maintain data integrity and reliability with integrated ECC.
• Protect DRAM memory shared by the processor and FPGA with an integrated memory protection unit.
• Enable system-level debug with Intel’s FPGA-adaptive debugging for unmatched visibility and control of the whole device.

Not All SoC FPGAs Are Created Equal. Architecture Matters.

Learn how to choose the right SoC FPGA for your application from our extensive set of resources, including a short series of videos from processor expert Jim Turley.

Cyclone V SoC FPGA Architecture

Cyclone® V SoC FPGAs offers a powerful dual-core ARM* Cortex*-A9 MPCore* processor surrounded by a rich set of peripherals and a hardened memory controller. The FPGA fabric, with up to 110K LEs (logic elements), is connected to the hard processor system (HPS) through a high-speed >100 Gbps interconnect backbone.