Intel® Stratix® 10 FPGA Applications

Delivering an unprecedented 2X performance, up to 70% lower power, up to 10.2 million LEs, and the highest level of system integration†, Intel® Stratix® 10 devices are uniquely positioned to address next-generation, high-performance systems in the most demanding applications including communications, data center acceleration, high-performance computing, radar processing, ASIC prototyping, and many more.

Data Center Acceleration

Cognitive Computing


High-performance accelerators

  • Up to 8.6 TFLOPS.
  • Highest fabric performance.
  • Highest memory bandwidth.

Algorithm flexibility

  • OpenCL™1platform.
  • Software front end for security and flow control with integrated ARM* Cortex*-A53 hard processor system.

Unique to Intel® Stratix® 10 Devices

  • First FPGA devices to support Intel® Ultra Path Interconnect (UPI) for direct coherent connection to Intel® Xeon® Scalable processor.
  • FPGA PCIe* hard IP with configuration up to Gen4 x16 at 16 Gbps.
  • HyperFlex FPGA Architecture delivers up to 1 GHz performance, enabling breakthroughs in computational throughput.
  • Hardened single-precision floating-point DSP block, compliant with IEEE 754 standard, delivers GPU-class floating performance at a fraction of the power.
  • Hardened AI Tensor Block tuned for common matrix-matrix or vector-matrix multiplications in AI acceleration applications resulting in up to 15X more INT82 throughput than standard DSP Block.
  • Secure cloud solutions using the security features.


Bridging and Aggregation

Enabling New Network Infrastructure


High throughput with power efficiency

  • Up to 10 TFLOPS 400G traffic manager with 600 million packet per second throughput.
  • Less than 1 watt per 10 Gbps.

Flexible, high-performance interconnect

  • Adaptable, scalable, and optimized IP portolio including 400G Ethernet.
  • Integrated processor for system monitoring and management.

Unique to Intel® Stratix® 10 Devices

  • fMAX over 700 MHz using the Intel® HyperFlex™ FPGA Architecture enabling 400G Ethernet.
  • 512 bit wide datapath running at 2X performance enables half-size IP compared to conventional architectures.

OTN/Data Center Interconnect

400 Gbit/s Muxponder for Metro / DCI



  • Four OTU4 line side interface.
    • OTL4.4.
    • GFEC.
    • ODUk/flex – ODU4 multiplexer.
  • 20 ‘any rate’ client interfaces.
    • 16 interfaces from 1GE to 25GE/32GFC
      Alternatively 4 x 100GE.
    • 4 interfaces of 1-14G.
  • Cross-connect.
    • Full add/drop connectivity between line-line and line-client.
    • Protection switching.

Optional Features

  • 128GFC client.
  • KP-FEC (544, 514) for clients.
  • PAM4 transceivers.

2.4 Tbit/s Switch/Muxponder for DCI



  • 2.4 Tbit/s cross-connect between Ethernet flows.
  • 1.2 Tbit/s FlexE muxponder/transponder.
  • (528,514,10) RS-FEC and (544,514,10) KP-FEC support.
  • Optical interfaces: FlexE server, 100GE, 25GE, 10GE.
  • FlexE configurable as 400G/200G+200G/100G+300G.
  • Cross-connect supports: 10/25/50/100GE flows.
  • Low power FEC Hard IP while providing fabric flexibility.

Unique to Intel® Stratix® 10 Devices

  • Heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles delivers 30G backplane support with a path to 58G data rates.
  • HyperFlex FPGA Architecture enables 2X performance resulting in significant IP size reduction.
  • Hardened single-precision floating-point DSP block, compliant with IEEE 754 standard, delivers GPU-class floating performance at a fraction of the power.
  • Secure cloud solutions using the security features.


Digitizing the Radar Front-End


Highest performance per watt

  • Up to 10 TFLOPS single-precision floating-point performance.
  • Up to 80 GFLOPS/Watt.

High-throughput front end

  • High number of simultaneous beams with high bandwidth.
  • Beam former IP.

Unique to Intel® Stratix® 10 Devices

  • Up to 10 TFLOPS of IEEE 754 compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power.
  • Cover fMAX up to 1 GHz enabling high throughput beam processing.

ASIC Prototyping and Emulation

Highest FPGA Fabric Capacity


Highest density for scalability

  • 10.2 million LE core fabric.

Debug productivity

  • Readback and writeback IP.

Highest I/O counts for flexibility

  • 2,300+ I/Os.

Integration with multiple fabric and transceiver chiplets

  • Intel® Embedded Multi-Die Interconnect Bridge (EMIB) technology.

Unique to Intel® Stratix® 10 Devices

  • Highest density enable customers to scale prototyping and emulation solution.
  • Highest I/O counts provide flexibility for design partitioning across multiple FPGAs.
  • Readback and writeback IP enhances debug productivity.

Cyber Security

Network Intrusion Detection and Prevention

400G Throughput Bump-in-the-Wire


Line rate analysis of data traffic

  • From 1G to 400G.
  • Implement Intrusion Prevention Systems (IPS) and Intrusion Detection Systems (IDS) on streaming traffic.


  • Security performed on traffic flows prior to entering network.
  • Continuous network monitoring or tagging of live traffic.

Unique to Intel® Stratix® 10 Devices

  • fMAX over 900 MHz allows monitoring of all supported protocols at line rates.
  • ARM* Cortex*-A53 processor enables direct interfacing with existing IT software.
  • Partial reconfiguration and OpenCL™ platform allow for easy rules updates.

Intel® Stratix® 10 FPGA Reference Links

Informazioni su prodotti e prestazioni

1OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

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