Intel® Stratix® 10 SX SoC FPGAs

Intel® Stratix® 10 SoCs, combine a quad-core ARM* Cortex*–A53 MPCore* hard processor system with the revolutionary Intel® Hyperflex™ FPGA Architecture to deliver the embedded performance, power efficiency, density, and system integration necessary for embedded applications.

See also: Intel® Stratix® 10 SX FPGAs Design Software, Design Store, Downloads, Documentation, Community, and Support

Intel® Stratix® 10 SX SoC FPGAs

FPGA SoC Intel® Stratix® 10 SX

View Intel® Stratix® 10 SX SoC FPGAs and find product specifications, features, applications and more.

View product table

8 Prodotti CONFRONTA TUTTI NON CONFRONTARE
Confronta
Nome prodotto
Stato
Data di lancio
Elementi logici (LE)
Blocchi di elaborazione del segnale digitale (DSP)
Memoria massima integrata
Opzioni di pacchetto
Prezzo
Intel® Stratix® 10 SX 650 FPGA Launched 2013 612000 1152 52 Mb F1152
Intel® Stratix® 10 SX 400 FPGA Launched 2013 378000 648 32 Mb F1152
Intel® Stratix® 10 SX 1100 FPGA Launched 2013 1325000 2592 114 Mb F1760
Intel® Stratix® 10 SX 850 FPGA Launched 2013 841000 2016 72 Mb F1760
Intel® Stratix® 10 SX 1650 FPGA Launched 2013 1624000 3145 122 Mb F1760, F2397
Intel® Stratix® 10 SX 2100 FPGA Launched 2013 2005000 3744 138 Mb F1760, F2397
Intel® Stratix® 10 SX 2500 FPGA Launched 2013 2422000 5011 208 Mb F1760, F2397, F2912
Intel® Stratix® 10 SX 2800 FPGA Launched 2013 2753000 5760 244 Mb F1760, F2397, F2912
Mostra di più Mostra di meno

Features & Benefits

View all features

Achieve High Levels of System Integration

Intel® Stratix® 10 SoCs empowers the USR in the ARM* ecosystem. ARM's next-generation 64-bit architecture (ARMv8) enabling enable hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The ARM* Cortex-A53* processor supports 32-bit execution mode and board support packages for popular operating system including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more.

Achieve High Designer Productivity with Optimized FPGA and SoC Design Software

New engine optimized for multi-million logic elements (LE) FPGA designs providing significant reduction in design iterations, Intel® Stratix® 10 SoC Virtual Platform to enable early software development and verification, and C-based design entry using the Intel® FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs. Heterogeneous debug, profiling, and whole chip visualization with Intel® FPGA SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition Toolkit.

Intel® Stratix® 10 SoC Block Diagram

HPS: Quad-core ARM* Cortex*-A53 Hard Processor System
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge

Feature

Description

Processor

Quad-core ARM* Cortex*–A53 MPCore* processor cluster up to 1.5 GHz

Coprocessors

Vector floating-point unit (VFPU) single and double precision, ARM* Neon* media processing engine for each processor

Level 1 Cache

32 KB L1 instruction cache with parity, 32 KB L1 data cache with error correction code (ECC)

Level 2 Cache

1 MB KB shared L2 cache with ECC

On-Chip Memory

256 KB on-chip RAM

System Memory Management Unit

System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric

Cache Coherency Unit

Provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the ARM* Cortex*–A53 MPCore* CPUs

Direct Memory Access (DMA) Controller

8-channel direct memory access (DMA)

Ethernet Media Access Controller (EMAC)

3X 10/100/1000 EMAC with integrated DMA

USB On-The-Go Controller (OTG)

2X USB OTG with integrated DMA

UART Controller

2X UART 16550 compatible

Serial Peripheral Interface (SPI) Controller

4X SPI

I2C Controller

5X I2C

SD/SDIO/MMC Controller

1X eMMC 4.5 with DMA and CE-ATA support

NAND Flash Controller

1X ONFI 1.0 or later 8 and 16-bit support

General-Purpose I/O (GPIO)

Maximum 48 software-programmable GPIO
Timers 4X general-purpose timers, 4X watchdog timers
System Manager Contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules
Reset Manager Resets signals based on reset requests from sources in the HPS and FPGA fabric, and software writing to the module reset control registers
Clock Manager Provides software-programmable clock control to configure all clocks generated in the HPS
Mostra di più Mostra di meno View all

Ecosystem

Intel® SoC FPGAs are ARM* processor-based and inherit the strength of the ARM* eco-system. Intel, our ecosystem partners, and the Intel® SoC FPGA user community provide a wide range of options to meet your SoC FPGA development needs.

See the ecosystem

Videos

Intel® Stratix® 10 Device Demo Videos

28G Transceivers

In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers that are connected via Intel's EMIB technology and operating at 28 Gbps backplane performance.

Watch video

Intel® Hyperflex™ FPGA Architecture

Intel® Hyperflex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the Fmax performance.1 This video shows a side-by-side comparison of an original design and a Hyper-Optimized design.

Watch video

PCIe* Gen3 DMA to DDR4 SDRAM

Intel® Stratix® 10 devices, which include PCI Express* (PCIe*) and memory controller hard intellectual property (IP) blocks, combined with Avalon® memory-mapped interface and direct memory access (DMA) functions to create a high-performance reference design.

Watch video

Mostra di più Mostra di meno

Samples and Ordering

Learn more about how to buy Intel® Programmable solutions, explore available development kits, and more.

Development Kits

Get information about hardware solutions and tools offered by Intel to accelerate the design process.

Powering FPGAs

See recommended Intel® Enpirion® Power Solutions and resources for powering Intel® FPGAs.

Ordering Codes

Decipher Intel® FPGA part numbers, including the significance of certain prefixes and package codes.

Where to Buy

Contact an Intel® Authorized Distributor today.

Confronta

Informazioni su prodotti e prestazioni

1

Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.it/benchmarks.