CPLD MAX® V

{"limitDisplayedContent":"showAll","collectionRelationTags":{"relations":{"OR":["etm-C29F58D8-B31D-4109-B8FC-F6D026341F6C","etm-9A05AA22-DCA0-413D-BFCE-F341DA4FFAA5"],"EXCLUDE":["etm-f6e0d09943a943d383e81b5f64a3956c","etm-3bb2fede81914ffabfb7e39c78121719","etm-98109f19d4f24b6dad7442422a995aee","etm-f98414c18285485aa46a8e4c3802bc70","etm-ececc448f2f54f0e87cdf5558856b275"],"Child":["732127"]},"featuredIds":[]},"collectionId":"653143","resultPerPage":15.0,"filters":[{"facetId":"ContentType","type":"ContentType","deprecated":true,"name":"ContentType","position":0},{"facetId":"guidetmC29F58D8B31D4109B8FCF6D026341F6C","field":"stm_10385_it","type":"hierarchical","basePath":"Primary Content Tagging","displayName":"MAX® V CPLDs","deprecated":false,"rootFilter":"guidetmC29F58D8B31D4109B8FCF6D026341F6C","rootPath":["Primary Content Tagging","Intel® FPGA","Dispositivi programmabili Intel®","CPLD e FPGA Intel® MAX®","CPLD MAX® V"],"position":1},{"facetId":"lastupdated","type":"lastupdated","deprecated":true,"name":"lastupdated","position":2}],"coveoRequestHardLimit":"1000","accessDetailsPagePath":"/content/www/us/en/secure/design/internal/access-details.html","cardView":false,"ignoreSoftware":true,"sorting":"Newest","defaultImagesPath":"/content/dam/www/public/us/en/images/uatable/default-icons","coveoMaxResults":5000,"fpgaFacetRootPaths":"{\"fpgadevicefamily\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Programmable Devices\"],\"quartusedition\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software\"],\"quartusaddon\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software - Add-ons\"],\"fpgaplatform\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® FPGA Platforms\"]}","newWrapperPageEnabled":true,"descendingSortingForNumericalFacetsName":"[\"Intel® Quartus® Prime Pro Edition\",\"Intel® Quartus® Prime Lite Edition\",\"Intel® Quartus® Prime Standard Edition\",\"Quartus® II Subscription Edition\",\"Quartus® II Web Edition\"]","columnsConfiguration":{"idColumn":false,"dateColumn":false,"versionColumn":false,"contentTypeColumn":false,"columnsMaxSize":0},"dynamicColumnsConfiguration":[{"name":"DynamicColumn_id","type":"id","gtv":"ID","width":60,"selected":true},{"name":"DynamicColumn_date","type":"date","gtv":"Data","width":60,"selected":true},{"name":"DynamicColumn_version","type":"version","gtv":"Versione","width":135,"selected":true}],"curatedFilter":[{"title":"Featured Documents","tags":[{"relationship":"AND","value":"Recommended","id":"etm-a065764d12404422a4010b8396828f63"}]},{"title":"Development Software","tags":[{"relationship":"AND","value":"Development Software","id":"etm-ebfe0f9272ba4af9989d1a08f7494bf0"}]},{"title":"Intellectual Property","tags":[{"relationship":"AND","value":"Intellectual Property","id":"etm-0b7580c08e2b4e9eacf848bf52b528e6"}]},{"title":"Datasheet Group","tags":[{"relationship":"OR","value":"Device Overviews","id":"etm-20ef38132a9243a0826bd1e320b198f9"},{"relationship":"OR","value":"Datasheets","id":"etm-d3b801521ba841da80fdd1a3aae06299"},{"relationship":"OR","value":"Errata","id":"etm-73cf3cc1679b467c94e69dbcdde7fc7f"},{"relationship":"AND","value":"Intel® FPGAs PPCH_L1_98836","id":"etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1"}]}],"updateCollateralMetadataEnabled":true}