Cyclone® V SX SoC FPGA
Cyclone® V SX FPGA is optimized for low system cost and power with integrated ARM® Cortex®-A9 MPCore Processor System for general logic and DSP applications.
Cyclone® V SX SoC FPGA
Benefits
Do More with Less Power, Design Time, and Cost
Built on TSMC's 28 nm low-power (28LP) process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more.
Logic Integration and Differentiation Capabilities
It offers an 8-input adaptive logic module (ALM) and variable-precision digital signal processing (DSP) blocks, allowing up to 13.59 megabits (Mb) of embedded memory.
Hard processor system (HPS) with integrated ARM® Cortex®-A9 MPCore processor
Tight integration of a dual-core ARM® Cortex®-A9 MPCore processor, hard IP, and an FPGA in a single Cyclone® V system-on-a-chip (SoC). It supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric.
Applications
Wireless: Wireless Backhaul
Integration simplifies system design: integrated 6G transceivers, PCIe hardware, Interoperability platform, and IP suite for common functions. Reduces operating costs: 40% lower power than prior generations, 88 mW power per channel, and cost-effective thermal cooling.
Autonomous Driving and InVehicle Experience (IVE)
Automotive-grade FPGAs and SoCs can be combined or used separately to enable applications such as gesture recognition, driver monitoring systems, and blind spot detection. They also provide flexibility, low latency, high performance-per-watt, functional safety, and security advantages for Advanced Driver Assistance System (ADAS)/AD applications like sensor ingest, pre-processing, and acceleration.
Key Features
Embedded Memory Blocks
- M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC).
- Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory.
General-purpose I/Os
- 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter.
- 400 MHz/800 Mbps external memory interface.
- On-chip termination (OCT).
- 3.3 V support with up to 16 mA drive strength.
External Memory Interface
In the Cyclone® V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices.
Hard Processor System (HPS)
The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multiport SDRAM memory controller.
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