Intel® Agilex™ I-Series SoC FPGAs
Intel® Agilex™ I-Series SoC FPGAs are optimized for applications which are bandwidth intensive and require high performance processor interface. Options to integrate Compute Express Link - the industry's first Cache and Memory coherent interconnect to Intel® Xeon® Scalable processors, PCIe* Gen 5 interface and transceiver tiles with data rates up to 112Gbps make the Intel® Agilex™ I-Series SoC FPGAs a compelling choice for applications which demand massive bandwidth and high performance to move, store, and process data.
See also: Intel® Agilex™ I-Series SoC FPGAs Design Software, Design Store, Downloads, Documentation, Community, and Support
Intel® Agilex™ I-Series SoC FPGAs
Acceleration from Edge to Cloud
Learn how Intel® Agilex™ FPGA and SoC family combine the power of heterogeneous architecture, transceiver leadership, and programmable software to deliver higher silicon integration, smaller form factor, and energy efficient compute acceleration for applications from the edge to cloud.
Features
Compute Express Link
With the Compute Express Link, Intel® Agilex™ FPGA and SoC family offers the industry’s first Cache and Memory coherent interconnect to Intel® Xeon® processors. This revolutionary FPGA interconnect will provide low latency and performance gains for memory intensive applications with massive data processing needs.
Transceiver Leadership
Intel® Agilex™ I-Series SoC FPGA family will continue Intel’s transceiver technology innovation and leadership with the 112 Gbps transceiver tile to support the bandwidth requirements in data center, enterprise, and networking applications. It will also include PCIe* Gen 5 x16 interface support to deliver 2X more bandwidth for massive data transfers compared to PCIe* Gen 4 x16 interface.
Hardened Protocol Support
Intel® Agilex™ FPGA and SoC family delivers optimal power, performance, and logic utilization efficiency by integrating hardened protocols for popular functions including 100/200/400G Ethernet, PCIe* Gen 4/5 interface, Interlaken, CPRI, JESD204B/C, and many more.
Secure Device Manager
A triple redundant Secure Device Manager (SDM) with built-in ECC will serve as the central command center for the entire FPGA. The SDM manages configuration, responses to SEU events, tamper detection, encryption, authentication, and oversees the boot order. Asymmetric key encryption in the SDM allows for Private root of trust on FPGA. This 2nd Generation SDM plays a pivotal role in securing data in public and private cloud, communication endpoints, and enterprise infrastructure systems.
Videos
Intel® Agilex™ FPGA and SoC Family
Watch this video to learn more about how Intel® Agilex™ FPGA and SoC family delivers customized connectivity, low latency, maximum data throughput, and customized acceleration by combining agility and flexibility to process, store, and move data for data-centric applications.
Intel® Agilex™ FPGA and SoC Architecture
Significant architectural improvements, DSP innovations, and fundamental changes in routing and layout combine to deliver up to 40% higher performance or 40% lower power1 with the Intel® Agilex™ FPGA and SoC family. Checkout the video to learn more!
112G PAM-4 Transceivers
Intel® Agilex™ FPGA and SoC family offers new levels of performance using Intel’s Advanced 10nm FinFET Process. 112Gbps serial transceiver links support demanding bandwidth requirements in next-generation data center, enterprise, and networking environments.
Documentation and Support
Find technical documentation, videos, and training courses for your Intel® Agilex™ device designs.
Related Links
Informazioni su prodotti e prestazioni
Questo confronto basato su FPGA famiglia di SoC Intel® Agilex™ rispetto a 10 FPGA Intel® Stratix® utilizza risultati di simulazione ed è soggetto a modifiche. Questo documento contiene informazioni su prodotti, servizi e/o processi in fase di sviluppo. Tutte le informazioni sono soggette a modifica senza preavviso. Contattare il proprio responsabile Intel per ottenere le più recenti previsioni, programmazioni, specifiche e roadmap.
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