F-Tile SDI II Intel® FPGA IP Design Example User Guide

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ID 710496
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Configure the SDI II Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design examples.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. To generate Example Design with Enable Active Video Protocol = AXIS-VVP Full, follow these steps:
    • For Quartus® Prime Pro Edition running in a Windows environment:
      1. Open " Nios® V Command Shell" from the Windows search path.
      2. Run "quartus" in Nios® V Command Shell to open Quartus® Prime Pro Edition.
    • For Quartus® Prime Pro Edition running in a Linux environment:
      1. cd to <Quartus installation path>/niosv/bin and run "niosv-shell".
      2. Run "quartus" to open Quartus® Prime Pro Edition.
  2. Create an empty project targeting Agilex™ 7 F-Tile device family and select the desired device.
  3. In the IP Catalog, locate and double-click SDI II Intel® FPGA IP . The IP Parameter Editor window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
  5. Click OK. The parameter editor appears.
  6. On the IP tab, select your desired IP settings. The generated design example is based on your settings.
  7. On the Design Example tab, select the desired parameter for the design example. Select Simulation to generate the testbench.
  8. For Target Development Kit, select the relevant FPGA development kit. You may change the target device using the Change Target Device parameter if your board revision does not match the grade of the default targeted device.
  9. Click Generate Example Design button to initiate the design generation.
Figure 4. Design Example Tab in SDI II IP Parameter Editor
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