"Pin Information for the IntelŽ CycloneŽ10 10CL025 Device Version 2019.03.29 Notes (1), (2)" Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Emulated LVDS Output Channel E144 (3) B1 VREFB1N0 IO "DATA1,ASDO" DIFFIO_L3n 6 B1 VREFB1N0 IO VREFB1N0 7 B1 VREFB1N0 IO "FLASH_nCE,nCSO" DIFFIO_L4p 8 B1 VREFB1N0 nSTATUS nSTATUS 9 B1 VREFB1N0 IO DPCLK0 DIFFIO_L6p 10 B1 VREFB1N0 IO DIFFIO_L6n 11 B1 VREFB1N0 IO DCLK 12 B1 VREFB1N0 IO DATA0 13 B1 VREFB1N0 nCONFIG nCONFIG 14 B1 VREFB1N0 TDI TDI 15 B1 VREFB1N0 TCK TCK 16 B1 VREFB1N0 TMS TMS 18 B1 VREFB1N0 TDO TDO 20 B1 VREFB1N0 nCE nCE 21 B1 VREFB1N0 CLK0 DIFFCLK_0p 22 B1 VREFB1N0 CLK1 DIFFCLK_0n 23 B2 VREFB2N0 CLK2 DIFFCLK_1p 24 B2 VREFB2N0 CLK3 DIFFCLK_1n 25 B2 VREFB2N0 IO DIFFIO_L8p 28 B2 VREFB2N0 IO VREFB2N0 31 B2 VREFB2N0 IO RUP1 32 B2 VREFB2N0 IO RDN1 33 B3 VREFB3N0 IO DIFFIO_B2p 39 B3 VREFB3N0 IO CDPCLK2 42 B3 VREFB3N0 IO PLL1_CLKOUTp 43 B3 VREFB3N0 IO PLL1_CLKOUTn 44 B3 VREFB3N0 IO VREFB3N0 46 B3 VREFB3N0 IO DIFFIO_B9n 49 B3 VREFB3N0 IO DIFFIO_B10n 50 B3 VREFB3N0 IO DIFFIO_B11p 51 B3 VREFB3N0 CLK15 DIFFCLK_6p 52 B3 VREFB3N0 CLK14 DIFFCLK_6n 53 B4 VREFB4N0 CLK13 DIFFCLK_7p 54 B4 VREFB4N0 CLK12 DIFFCLK_7n 55 B4 VREFB4N0 IO DIFFIO_B16p 58 B4 VREFB4N0 IO DIFFIO_B17p 59 B4 VREFB4N0 IO DIFFIO_B17n 60 B4 VREFB4N0 IO VREFB4N0 65 B4 VREFB4N0 IO RUP2 66 B4 VREFB4N0 IO RDN2 67 B4 VREFB4N0 IO CDPCLK3 DIFFIO_B23n 68 B4 VREFB4N0 IO DIFFIO_B24p 69 B4 VREFB4N0 IO PLL4_CLKOUTp 71 B4 VREFB4N0 IO PLL4_CLKOUTn 72 B5 VREFB5N0 IO RUP3 76 B5 VREFB5N0 IO RDN3 77 B5 VREFB5N0 IO VREFB5N0 80 B5 VREFB5N0 IO DIFFIO_R11p 83 B5 VREFB5N0 IO DPCLK6 DIFFIO_R10p 85 B5 VREFB5N0 IO DEV_OE DIFFIO_R9n 86 B5 VREFB5N0 IO DEV_CLRn DIFFIO_R9p 87 B5 VREFB5N0 CLK7 DIFFCLK_3n 88 B5 VREFB5N0 CLK6 DIFFCLK_3p 89 B6 VREFB6N0 CLK5 DIFFCLK_2n 90 B6 VREFB6N0 CLK4 DIFFCLK_2p 91 B6 VREFB6N0 CONF_DONE CONF_DONE 92 B6 VREFB6N0 MSEL0 MSEL0 94 B6 VREFB6N0 MSEL1 MSEL1 96 B6 VREFB6N0 MSEL2 MSEL2 97 B6 VREFB6N0 IO INIT_DONE DIFFIO_R5n 98 B6 VREFB6N0 IO CRC_ERROR DIFFIO_R5p 99 B6 VREFB6N0 IO 100 B6 VREFB6N0 IO nCEO DIFFIO_R4n 101 B6 VREFB6N0 IO CLKUSR DIFFIO_R4p 103 B6 VREFB6N0 IO VREFB6N0 105 B6 VREFB6N0 IO DIFFIO_R1n 106 B7 VREFB7N0 IO DIFFIO_T22p 111 B7 VREFB7N0 IO PLL2_CLKOUTn 112 B7 VREFB7N0 IO PLL2_CLKOUTp 113 B7 VREFB7N0 IO RUP4 114 B7 VREFB7N0 IO RDN4 115 B7 VREFB7N0 IO VREFB7N0 119 B7 VREFB7N0 IO DIFFIO_T19n 120 B7 VREFB7N0 IO DIFFIO_T17p 121 B7 VREFB7N0 IO DIFFIO_T13p 125 B7 VREFB7N0 CLK8 DIFFCLK_5n 126 B7 VREFB7N0 CLK9 DIFFCLK_5p 127 B8 VREFB8N0 CLK10 DIFFCLK_4n 128 B8 VREFB8N0 CLK11 DIFFCLK_4p 129 B8 VREFB8N0 IO DATA2 DIFFIO_T10n 132 B8 VREFB8N0 IO DATA3 DIFFIO_T10p 133 B8 VREFB8N0 IO DATA4 DIFFIO_T9p 135 B8 VREFB8N0 IO VREFB8N0 136 B8 VREFB8N0 IO DATA5 137 B8 VREFB8N0 IO DIFFIO_T2p 141 B8 VREFB8N0 IO CDPCLK7 142 B8 VREFB8N0 IO PLL3_CLKOUTn 143 B8 VREFB8N0 IO PLL3_CLKOUTp 144 GND 19 GND 27 GND 41 GND 48 GND 57 GND 63 GND 82 GND 95 GND 118 GND 123 GND 131 GND 140 GND 4 GND 79 GND 30 GND 64 GND 104 GND 110 GNDA1 36 GNDA2 108 GNDA3 2 GNDA4 74 VCCD_PLL1 37 VCCD_PLL2 109 VCCD_PLL3 1 VCCD_PLL4 73 VCCIO1 17 VCCIO2 26 VCCIO3 40 VCCIO3 47 VCCIO4 56 VCCIO4 62 VCCIO5 81 VCCIO6 93 VCCIO7 117 VCCIO7 122 VCCIO8 130 VCCIO8 139 VCCA1 35 VCCA2 107 VCCA3 3 VCCA4 75 VCCINT 5 VCCINT 29 VCCINT 34 VCCINT 38 VCCINT 45 VCCINT 61 VCCINT 70 VCCINT 78 VCCINT 84 VCCINT 102 VCCINT 116 VCCINT 124 VCCINT 134 VCCINT 138 Notes: "(1) If the p pin or n pin is not available for the package, the particular differential pair is not supported." "(2) For more information about pin definition and pin connection guidelines, refer to the " Cyclone 10 LP Device Family Pin Connection Guidelines. (3) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. "This exposed pad is used for electrical connectivity, and not for thermal purposes." "Pin Information for the IntelŽ CycloneŽ10 10CL025 Device Version 2019.03.29 Notes (1), (2)" Bank Number VREF Pin Name/Function Optional Function(s) Configuration Function Emulated LVDS Output Channel U256 B1 VREFB1N0 IO CDPCLK0 B1 B1 VREFB1N0 IO DIFFIO_L3p C2 B1 VREFB1N0 IO "DATA1,ASDO" DIFFIO_L3n C1 B1 VREFB1N0 IO VREFB1N0 F3 B1 VREFB1N0 IO "FLASH_nCE,nCSO" DIFFIO_L4p D2 B1 VREFB1N0 IO DIFFIO_L4n D1 B1 VREFB1N0 nSTATUS nSTATUS F4 B1 VREFB1N0 IO DPCLK0 DIFFIO_L6p G2 B1 VREFB1N0 IO DIFFIO_L6n G1 B1 VREFB1N0 IO DCLK H1 B1 VREFB1N0 IO DATA0 H2 B1 VREFB1N0 nCONFIG nCONFIG H5 B1 VREFB1N0 TDI TDI H4 B1 VREFB1N0 TCK TCK H3 B1 VREFB1N0 TMS TMS J5 B1 VREFB1N0 TDO TDO J4 B1 VREFB1N0 nCE nCE J3 B1 VREFB1N0 CLK0 DIFFCLK_0p E2 B1 VREFB1N0 CLK1 DIFFCLK_0n E1 B2 VREFB2N0 CLK2 DIFFCLK_1p M2 B2 VREFB2N0 CLK3 DIFFCLK_1n M1 B2 VREFB2N0 IO DIFFIO_L7p J2 B2 VREFB2N0 IO DIFFIO_L7n J1 B2 VREFB2N0 IO DIFFIO_L10p K2 B2 VREFB2N0 IO DIFFIO_L10n K1 B2 VREFB2N0 IO DPCLK1 DIFFIO_L11p L2 B2 VREFB2N0 IO DIFFIO_L11n L1 B2 VREFB2N0 IO VREFB2N0 L3 B2 VREFB2N0 IO DIFFIO_L13p N2 B2 VREFB2N0 IO DIFFIO_L13n N1 B2 VREFB2N0 IO RUP1 K5 B2 VREFB2N0 IO RDN1 L4 B2 VREFB2N0 IO CDPCLK1 R1 B2 VREFB2N0 IO DIFFIO_L15p P2 B2 VREFB2N0 IO DIFFIO_L15n P1 B3 VREFB3N0 IO DIFFIO_B1p N3 B3 VREFB3N0 IO DIFFIO_B1n P3 B3 VREFB3N0 IO DIFFIO_B2p R3 B3 VREFB3N0 IO DIFFIO_B2n T3 B3 VREFB3N0 IO CDPCLK2 T2 B3 VREFB3N0 IO PLL1_CLKOUTp R4 B3 VREFB3N0 IO PLL1_CLKOUTn T4 B3 VREFB3N0 IO DIFFIO_B4p N5 B3 VREFB3N0 IO DIFFIO_B4n N6 B3 VREFB3N0 IO M6 B3 VREFB3N0 IO VREFB3N0 P6 B3 VREFB3N0 IO DPCLK2 DIFFIO_B5p M7 B3 VREFB3N0 IO DIFFIO_B6p R5 B3 VREFB3N0 IO DIFFIO_B6n T5 B3 VREFB3N0 IO DIFFIO_B7p R6 B3 VREFB3N0 IO DIFFIO_B7n T6 B3 VREFB3N0 IO L7 B3 VREFB3N0 IO DIFFIO_B8p R7 B3 VREFB3N0 IO DPCLK3 DIFFIO_B8n T7 B3 VREFB3N0 IO DIFFIO_B9n L8 B3 VREFB3N0 IO DIFFIO_B10n M8 B3 VREFB3N0 IO DIFFIO_B11p N8 B3 VREFB3N0 IO DIFFIO_B12n P8 B3 VREFB3N0 CLK15 DIFFCLK_6p R8 B3 VREFB3N0 CLK14 DIFFCLK_6n T8 B4 VREFB4N0 CLK13 DIFFCLK_7p R9 B4 VREFB4N0 CLK12 DIFFCLK_7n T9 B4 VREFB4N0 IO DIFFIO_B14n N9 B4 VREFB4N0 IO DIFFIO_B16p R10 B4 VREFB4N0 IO DPCLK4 DIFFIO_B16n T10 B4 VREFB4N0 IO DIFFIO_B17p R11 B4 VREFB4N0 IO DIFFIO_B17n T11 B4 VREFB4N0 IO DIFFIO_B18p R12 B4 VREFB4N0 IO DIFFIO_B18n T12 B4 VREFB4N0 IO DPCLK5 P9 B4 VREFB4N0 IO VREFB4N0 P11 B4 VREFB4N0 IO DIFFIO_B20p R13 B4 VREFB4N0 IO DIFFIO_B20n T13 B4 VREFB4N0 IO RUP2 M10 B4 VREFB4N0 IO RDN2 N11 B4 VREFB4N0 IO DIFFIO_B23p T14 B4 VREFB4N0 IO CDPCLK3 DIFFIO_B23n T15 B4 VREFB4N0 IO DIFFIO_B24p N12 B4 VREFB4N0 IO PLL4_CLKOUTp P14 B4 VREFB4N0 IO PLL4_CLKOUTn R14 B5 VREFB5N0 IO RUP3 N14 B5 VREFB5N0 IO RDN3 P15 B5 VREFB5N0 IO CDPCLK4 DIFFIO_R15n P16 B5 VREFB5N0 IO DIFFIO_R15p R16 B5 VREFB5N0 IO DIFFIO_R13n N16 B5 VREFB5N0 IO DIFFIO_R13p N15 B5 VREFB5N0 IO VREFB5N0 L14 B5 VREFB5N0 IO DIFFIO_R12p L13 B5 VREFB5N0 IO DIFFIO_R11n L16 B5 VREFB5N0 IO DIFFIO_R11p L15 B5 VREFB5N0 IO DIFFIO_R10n K16 B5 VREFB5N0 IO DPCLK6 DIFFIO_R10p K15 B5 VREFB5N0 IO DEV_OE DIFFIO_R9n J16 B5 VREFB5N0 IO DEV_CLRn DIFFIO_R9p J15 B5 VREFB5N0 IO DIFFIO_R8n J14 B5 VREFB5N0 IO DIFFIO_R7n J13 B5 VREFB5N0 CLK7 DIFFCLK_3n M16 B5 VREFB5N0 CLK6 DIFFCLK_3p M15 B6 VREFB6N0 CLK5 DIFFCLK_2n E16 B6 VREFB6N0 CLK4 DIFFCLK_2p E15 B6 VREFB6N0 CONF_DONE CONF_DONE H14 B6 VREFB6N0 MSEL0 MSEL0 H13 B6 VREFB6N0 MSEL1 MSEL1 H12 B6 VREFB6N0 MSEL2 MSEL2 G12 B6 VREFB6N0 IO INIT_DONE DIFFIO_R5n G16 B6 VREFB6N0 IO CRC_ERROR DIFFIO_R5p G15 B6 VREFB6N0 IO F13 B6 VREFB6N0 IO nCEO DIFFIO_R4n F16 B6 VREFB6N0 IO CLKUSR DIFFIO_R4p F15 B6 VREFB6N0 IO DPCLK7 B16 B6 VREFB6N0 IO VREFB6N0 F14 B6 VREFB6N0 IO D16 B6 VREFB6N0 IO D15 B6 VREFB6N0 IO CDPCLK5 DIFFIO_R1n C16 B6 VREFB6N0 IO DIFFIO_R1p C15 B7 VREFB7N0 IO DIFFIO_T24n C14 B7 VREFB7N0 IO DIFFIO_T24p D14 B7 VREFB7N0 IO DIFFIO_T23n D11 B7 VREFB7N0 IO CDPCLK6 DIFFIO_T23p D12 B7 VREFB7N0 IO DIFFIO_T22n A13 B7 VREFB7N0 IO DIFFIO_T22p B13 B7 VREFB7N0 IO PLL2_CLKOUTn A14 B7 VREFB7N0 IO PLL2_CLKOUTp B14 B7 VREFB7N0 IO RUP4 E11 B7 VREFB7N0 IO RDN4 E10 B7 VREFB7N0 IO DIFFIO_T21n A12 B7 VREFB7N0 IO DIFFIO_T21p B12 B7 VREFB7N0 IO DIFFIO_T20n A11 B7 VREFB7N0 IO DIFFIO_T20p B11 B7 VREFB7N0 IO VREFB7N0 C11 B7 VREFB7N0 IO DIFFIO_T19n A15 B7 VREFB7N0 IO DPCLK8 DIFFIO_T17p F9 B7 VREFB7N0 IO DIFFIO_T16n A10 B7 VREFB7N0 IO DIFFIO_T16p B10 B7 VREFB7N0 IO DIFFIO_T15n C9 B7 VREFB7N0 IO DIFFIO_T15p D9 B7 VREFB7N0 IO DPCLK9 DIFFIO_T13p E9 B7 VREFB7N0 CLK8 DIFFCLK_5n A9 B7 VREFB7N0 CLK9 DIFFCLK_5p B9 B8 VREFB8N0 CLK10 DIFFCLK_4n A8 B8 VREFB8N0 CLK11 DIFFCLK_4p B8 B8 VREFB8N0 IO DPCLK10 DIFFIO_T11p C8 B8 VREFB8N0 IO D8 B8 VREFB8N0 IO DATA2 DIFFIO_T10n E8 B8 VREFB8N0 IO DATA3 DIFFIO_T10p F8 B8 VREFB8N0 IO DIFFIO_T9n A7 B8 VREFB8N0 IO DATA4 DIFFIO_T9p B7 B8 VREFB8N0 IO VREFB8N0 C6 B8 VREFB8N0 IO DPCLK11 DIFFIO_T7n A6 B8 VREFB8N0 IO DIFFIO_T7p B6 B8 VREFB8N0 IO DATA5 E7 B8 VREFB8N0 IO DATA6 DIFFIO_T6p E6 B8 VREFB8N0 IO DATA7 DIFFIO_T5n A5 B8 VREFB8N0 IO DIFFIO_T5p B5 B8 VREFB8N0 IO DIFFIO_T4n D6 B8 VREFB8N0 IO DIFFIO_T3n A4 B8 VREFB8N0 IO DIFFIO_T3p B4 B8 VREFB8N0 IO DIFFIO_T2n A2 B8 VREFB8N0 IO DIFFIO_T2p A3 B8 VREFB8N0 IO CDPCLK7 B3 B8 VREFB8N0 IO PLL3_CLKOUTn C3 B8 VREFB8N0 IO PLL3_CLKOUTp D3 GND H7 GND H8 GND H9 GND H10 GND J7 GND J8 GND J9 GND J10 GND F6 GND F10 GND J11 GND K8 GND K6 GND L9 GND L10 GND L11 GND K12 GND G11 GND B2 GND B15 GND C5 GND C12 GND D7 GND D10 GND E4 GND E13 GND G4 GND G13 GND K4 GND K13 GND M4 GND M13 GND N7 GND N10 GND P5 GND P12 GND R2 GND R15 GND H16 GND H15 GND D5 GND F1 GND F2 GND G5 GNDA1 M5 GNDA2 E12 GNDA3 E5 GNDA4 M12 VCCD_PLL1 N4 VCCD_PLL2 D13 VCCD_PLL3 D4 VCCD_PLL4 N13 VCCIO1 E3 VCCIO1 G3 VCCIO2 K3 VCCIO2 M3 VCCIO3 P4 VCCIO3 P7 VCCIO3 T1 VCCIO4 P10 VCCIO4 P13 VCCIO4 T16 VCCIO5 K14 VCCIO5 M14 VCCIO6 E14 VCCIO6 G14 VCCIO7 A16 VCCIO7 C10 VCCIO7 C13 VCCIO8 A1 VCCIO8 C4 VCCIO8 C7 VCCA1 L5 VCCA2 F12 VCCA3 F5 VCCA4 L12 VCCINT F7 VCCINT F11 VCCINT G6 VCCINT G7 VCCINT G8 VCCINT G9 VCCINT G10 VCCINT H6 VCCINT H11 VCCINT J6 VCCINT K7 VCCINT K11 VCCINT L6 VCCINT K9 VCCINT K10 VCCINT M9 VCCINT M11 VCCINT J12 Notes: "(1) If the p pin or n pin is not available for the package, the particular differential pair is not supported." "(2) For more information about pin definition and pin connection guidelines, refer to the " Cyclone 10 LP Device Family Pin Connection Guidelines.