Release Notes For ModelSim Intel FPGA 2021.1 Feb 02 2021 Copyright 1991-2021 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. 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End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support ModelSim Intel FPGA is supported by Intel + World-Wide-Web Support [1]http://www.altera.com/mySupport _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2021.1 * [4]Base Product Specifications in 2021.1 * [5]Compatibility Issues with Release 2021.1 * [6]General Defects Repaired in 2021.1 * [7]SystemVerilog Defects Repaired in 2021.1 * [8]VHDL Defects Repaired in 2021.1 * [9]Mixed Language Defects Repaired in 2021.1 * [10]VHDL Enhancements in 2021.1 * [11]Document Revision History in 2021.1 _______________________________________________________________________ Key Information * Starting 2021.1 release, Redhat Enterprise Linux (RHEL) 6 platform and Suse Enterprise Linux (SLES) 11 will not be supported. * QSIM-64029 - There is no licensing change between 2020.x and 2021.1. However, if you are migrating to 2021.1 from a release older than 2020.1, please note that release 2021.1 uses FLEXnet v11.16.4.0. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.16.4.0. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.16.4.0 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to MSL v2020_1 with MGLS v9.23_5.5.0 and PCLS v9.23_5.3.0 In summary, this release uses the following license versions: + FLEXnet v11.16.4.0 + MSL v2020_1 + MGLS v9.23_5.5.0 + PCLS v9.23_5.3.0 * QSIM-62239 - For newly supported operating systems, like RHEL8, it is required to have the libnsl-devel package installed on the system to have the cosim functionality work as expected. * QSIM-67636 - For newly supported operating systems, like RHEL8, a linking error "[12]liblto_plugin.so: wrong ELF class: ELFCLASS32" might show up while building 32-bit libraries when using GCC versions other than the Versions we officially support. To fix/workaround this error, the flag '-fno-use-linker-plugin' should be passed to the linker command line. This applies to: + 'sccom' when using user specified GCC installation other than the supported ones + Using the shipped GCC executables directly to build 32-bit libraries/executables (using gcc/g++ commands). * QSIM-523 - SystemC/GCC changes starting 2021.1 + SystemC is now supported for the win64 platform + SystemC/DPI/PLI/VPI/FLI default compiler (MinGW GCC) for Windows, both win32 and win64, has been upgraded to 7.4.0 + MinGW GCC 4.2.1 for win32 and MinGW GCC 4.5.0 for win64 are no longer supported and will no longer be distributed with the release + Warnings may be emitted when %ll specifiers for long long 64 bit wide types are used with printf/scanf functions families on Windows when MinGW GCC 7.4.0 is being used + To suppress those warnings, the flag __USE_MINGW_ANSI_STDIO should be defined and set to 1 by passing -D__USE_MINGW_ANSI_STDIO=1 command line option QSIM-57794 - When Visual Studio 2017 is being used for C compilation, compilation errors due to missing printf/scanf functions families definitions may appear. To fix this issue #include should be added for the printf/scanf function families definitions to be available. _______________________________________________________________________ Release Announcements in 2021.1 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. _______________________________________________________________________ Base Product Specifications in 2021.1 * [Supported Platforms] Linux RHEL 7 x86/x86-64 Linux RHEL 8 x86/x86-64 Linux SLES 12 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-7.4.0-linux/gcc-7.4.0-linux_x86_64 gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64 gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64 gcc-7.4.0-mingw32vc15 gcc-7.4.0-mingw64vc15 [OVL (shipped with product)] v2.8.1 [VHDL OSVVM (shipped with product)] v2014.07 [VHDL UVVM (shipped with product)] UVVM v2019.11.25 [Licensing] FLEXnet v11.16.4.0 MSL v2020_1 MGLS v9.23_5.5.0 PCLS v9.23.5.3.0 _______________________________________________________________________ Compatibility Issues with Release 2021.1 SystemVerilog Compatibility * QSIM-62783 - (source) Vlog and vopt handled cases where a class had the same name as a package incorrectly in some cases. Given this example: package P ; typedef logic type1_t; class P; typedef logic type2_t; endclass endpackage import P::*; // Import in $unit scope makes class named "P" potentially visible module top; P::type1_t i; // This should be an error because "P" should reference the class P::type2_t j; // This should resolve to the type in class "P" endmodule The correct behavior is to report an error for P::type1_t and accept P::type2_t, but previous releases reversed that behavior. * QSIM-62590 - (source) In some cases, a randomize() call with in-line constraints, if the constraint symbol is not declared, it would insert dummy symbol instead, this now flags an error. VHDL Compatibility * QSIM-67598 - (source) Added error number 1624 to vcom and vopt to warn the user if a generic map is present on a component instantiation where the component has no generic list. Previous versions silently ignored the generic map. A warning is now generated by default. This should really be an error but for compatibility with previous releases it is only a warning an the generic map is still ignored. * QSIM-61007 - (results) It is not legal to connect ports in a port map with sub-element association to OPEN, even if all sub-elements are OPEN. This enhancement allows for unconstrained ports to be associated with sub-elements as long as all sub-elements associated to OPEN. This is to allow the unconstrained port to be given a constraint. Statements like PORT MAP( OUT(1) => OPEN) -- Constrains out to (1 to 1) PORT MAP( OUT(1 to 2) => OPEN) -- Constrains out to ( 1 to 2) Note that the direction of the unconstrained port is the direction of the index range subtype and is usually TO not DOWNTO. Mixed Language Compatibility * QSIM-67008 - (results) VHDL external names now do case insensitive name look up in System Verilog scopes. Previously it used the case of the identifiers that was in the VHDL code, which is incorrect. Because of this external names may resolve differently if names only differed in case. _______________________________________________________________________ General Defects Repaired in 2021.1 * QSIM-55060 - Running vopt to re-generate an existing optimized design after the work library had been moved in the file system would sometimes produce an error message involving the original file pathnames. The behavior has been fixed, and vopt will now re-generate the optimized design. _______________________________________________________________________ SystemVerilog Defects Repaired in 2021.1 * [nodvtid] - Vsim could sometimes give this error when declaring an out-of-body class function where the return type referenced another parameterized class using "classname::" Error: foo.sv(12): Questa has encountered an unexpected internal error: ../../src/vlog/vgencode.c(225). Please contact Questa support at [13]http://supportnet.mentor.com/ * QSIM-62783 - (source) Vlog and vopt handled cases where a class had the same name as a package incorrectly in some cases. Given this example: package P ; typedef logic type1_t; class P; typedef logic type2_t; endclass endpackage import P::*; // Import in $unit scope makes class named "P" potentially visible module top; P::type1_t i; // This should be an error because "P" should reference the class P::type2_t j; // This should resolve to the type in class "P" endmodule The correct behavior is to report an error for P::type1_t and accept P::type2_t, but previous releases reversed that behavior. * QSIM-62590 - (source) In some cases, a randomize() call with in-line constraints, if the constraint symbol is not declared, it would insert dummy symbol instead, this now flags an error. * QSIM-64132 - Vlog sometimes gave incorrect errors like: ** Error: while parsing file test.sv(50): Failed to find the name 'get_type' in scope 'tpkg' For names like 'pkg::typename::get_type() where "typename" is a typedef name resolving to a class. * QSIM-64922 - Vlog reported the error: ** Error: test.sv(7) Illegal reference to an interface type C::Intf in implements clause. In cases where "C" was a parameterized class type and 'Intf" was a typedef name referenceing an interface class. * QSIM-66870 - Vopt would generate an error like: ** Error: test.sv(51): Questa has encountered an unexpected internal error: ../../src/vlog/vgencode.c(99). When a derived class referenced the name of a class that is nested in the superclass. * QSIM-66663 - User will start getting error if array pattern key is not constant expression in assignment pattern. * QSIM-67450 - An error is now reported when a virtual method of an object or built-in method are used in event control expressions. An error is also now reported when a wait statement's return type is non-singular. These changes reflect LRM 9.4.2. _______________________________________________________________________ VHDL Defects Repaired in 2021.1 * QSIM-62149 - Using VHDL-2008, vopt would crash if an array of whose element subtype is not fully constrained is sliced. This would occur if the value of the slice is needed for elaboration. * QSIM-62768 - When using the -skip or -just option, comments that are followed by an empty line, would cause vcom to start processing a design unit's source early. This could result in compile time errors. * QSIM-65962 - During compilation with the -autoorder and -quiet switches, if semantic errors were encountered during the refresh phase, the errors would not be printed. This behavior is incorrect, and now all errors are printed, though other compilation logging messages are suppressed. * QSIM-66278 - Large data structures that take over 2Gbytes of space would crash if default initialization is used. For this to happen the default value for all fields in the data structure must be 0 or NULL. Explicitly initializing the object will work around the issue. * QSIM-67012 - Generic maps on subprogram instantiation declarations could associate non-object values with generics representing objects without emitting warning 1049. This warning is emitted in generic maps of all other instantiation forms, however. The compiler has been fixed to emit warnings when non-object values are associated with objects in generics maps of subprogram instantiation declarations. * QSIM-67598 - (source) Added error number 1624 to vcom and vopt to warn the user if a generic map is present on a component instantiation where the component has no generic list. Previous versions silently ignored the generic map. A warning is now generated by default. This should really be an error but for compatibility with previous releases it is only a warning an the generic map is still ignored. * QSIM-67153 - Simulation of a VHDL-2008 design containing instantiation of a package in which there is a declaration of a protected type within just the package body could cause a crash, due to incorrect code generation by the compiler. When the simulator crash occurs, it will happen during the design elaboration phase of simulation. There are no compiler or simulation switches that can inhibit this error. The compiler has been fixed to correctly generate code in this situation. _______________________________________________________________________ Mixed Language Defects Repaired in 2021.1 * QSIM-64244 - When Verilog instantiates a VHDL design unit, processing for connectivity analysis under the -rnm vopt switch did not correctly handle ports associated by-name. * QSIM-67008 - (results) VHDL external names now do case insensitive name look up in System Verilog scopes. Previously it used the case of the identifiers that was in the VHDL code, which is incorrect. Because of this external names may resolve differently if names only differed in case. _______________________________________________________________________ VHDL Enhancements in 2021.1 * QSIM-61007 - (results) It is not legal to connect ports in a port map with sub-element association to OPEN, even if all sub-elements are OPEN. This enhancement allows for unconstrained ports to be associated with sub-elements as long as all sub-elements associated to OPEN. This is to allow the unconstrained port to be given a constraint. Statements like PORT MAP( OUT(1) => OPEN) -- Constrains out to (1 to 1) PORT MAP( OUT(1 to 2) => OPEN) -- Constrains out to ( 1 to 2) Note that the direction of the unconstrained port is the direction of the index range subtype and is usually TO not DOWNTO. _______________________________________________________________________ Document Revision History in 2021.1 * Revision - Changes - Status/Date + 6.0 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/January 2021 * Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the document source. * Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available on Support Center (http://support.mentor.com).