Design guide: Intel® Xeon® processor and Intel® E7500/E7501 Chipset Compatible Platform.
Describes the component layout, baseboard requirements, platform clock, routing guidelines, hub interface, power delivery, debug tools, I/O Controller Hub 3, and more for the Intel® Xeon™ processor and Intel® E7500/E7501 Chipset compatible platform.
Intel® Xeon® Processor with 512-KB L2 Cache and Intel® E7500 Chipset Platform Design Guide with layout/routing guidelines, EMI/Mechanical design.
Discusses layout and routing guidelines, power delivery, hub interface, and EMI and mechanical design considerations for the Intel® Xeon® processor with 512-KB L2 Cache and Intel® E7500 chipset platform.
Intel® 6700PXH 64-bit PCI Hub device and documentation errata, specification clarifications, and changes.
This document is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
This datasheet is intended for Original Equipment Manufacturers and BIOS vendors that create ICH3-Server based products. This datasheet assumes a working knowledge of the vocabulary and principles of USB, IDE, AC ’97, SMBus, PCI, ACPI, and LPC.
Specification Update, 2006: Intel® 82801CA I/O Controller Hub 3 (ICH3-S), clarifications, changes, and documentation errata.
Specification updates for the Intel® 82801CA I/O Controller Hub 3 (ICH3-S), including device and documentation errata, specification clarification, and changes.
Intel® 82801DB I/O Controller Hub 4 (ICH4).
Covers descriptions, registers, mapping and more for the Intel® 82801DB I/O Controller Hub 4 (ICH4).
Thermal and Mechanical Design Guide: Intel® 82801EB I/O Controller Hub 5 and Intel® 82801EB I/O Controller Hub 5 R.
Discusses package, thermal and power specifications, thermal metrology, and thermal solutions for the Intel® 82801EB I/O Controller Hub 5 and Intel® 82801EB I/O Controller Hub 5 R.