PCI Express* (PCIe*) 3.0 Accelerator Features
Introduction
In recent years there has been a trend towards offloading compute-intensive workloads to specialized devices referred to as “accelerators.” These accelerators are used to improve platform performance in key computation (financial services), visualization (advanced gaming and workstations), content processing (Crypto and XML acceleration), and intelligent I/O applications. Two notable changes have contributed to this trend. First, the accelerators have benefited from Moore’s law which has given rise to extremely powerful engines which are increasingly multi-core/multi-thread/multi-card devices. Second, the accelerators are becoming increasingly programmable.
Although the development of specialized application accelerators had been going on for some time, there was no common standard hardware attach point and no common software architecture or programming model. The solution space was very fragmented, and as the number of applications started increasing an industry framework that economically and efficiently enables specialized acceleration became highly desirable. This had been recognized by Intel and IBM who, in mid-2006, started an initiative called “Geneseo.” Its goal was to enhance PCI Express*, which was already an industry mainstream I/O interconnect standard, with capabilities needed by accelerators. Intel and IBM developed a proposal for a set of extensions to the PCI Express* (PCIe*) Specification Rev 2.0. Although the initial requirements that drove the proposal were derived from accelerator applications, the extensions are general in nature and fit very well within the scalable architecture framework of PCIe. This proposal has now been adopted by the PCI SIG as a base for PCIe 3.0.
Note that Intel’s strategy for supporting accelerator applications extends beyond PCIe to include system interconnects, that is FSB (short term) and QPI (long term) as well as to address platform software infrastructure through a program initiative called QuickAssist.
Read the full PCI Express* 3.0 Accelerator Features.
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PCI Express* (PCIe*) 3.0 Accelerator Features
Introduction
In recent years there has been a trend towards offloading compute-intensive workloads to specialized devices referred to as “accelerators.” These accelerators are used to improve platform performance in key computation (financial services), visualization (advanced gaming and workstations), content processing (Crypto and XML acceleration), and intelligent I/O applications. Two notable changes have contributed to this trend. First, the accelerators have benefited from Moore’s law which has given rise to extremely powerful engines which are increasingly multi-core/multi-thread/multi-card devices. Second, the accelerators are becoming increasingly programmable.
Although the development of specialized application accelerators had been going on for some time, there was no common standard hardware attach point and no common software architecture or programming model. The solution space was very fragmented, and as the number of applications started increasing an industry framework that economically and efficiently enables specialized acceleration became highly desirable. This had been recognized by Intel and IBM who, in mid-2006, started an initiative called “Geneseo.” Its goal was to enhance PCI Express*, which was already an industry mainstream I/O interconnect standard, with capabilities needed by accelerators. Intel and IBM developed a proposal for a set of extensions to the PCI Express* (PCIe*) Specification Rev 2.0. Although the initial requirements that drove the proposal were derived from accelerator applications, the extensions are general in nature and fit very well within the scalable architecture framework of PCIe. This proposal has now been adopted by the PCI SIG as a base for PCIe 3.0.
Note that Intel’s strategy for supporting accelerator applications extends beyond PCIe to include system interconnects, that is FSB (short term) and QPI (long term) as well as to address platform software infrastructure through a program initiative called QuickAssist.
Read the full PCI Express* 3.0 Accelerator Features.
