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8 C 7 6 5 4 3 82575 REFERENCE DESIGN (SERDES/FIBER) 2 1 C B A PAGE INDEX 1 - TITLE PAGE 2 - FUNCTIONAL BLOCK DIAGRAM 3 - 82575 MDI, LEDS, CRYSTAL, SERDES, SFP, NCSI, SMBUS, EEPROM AND FLASH 4 - 82575 VCC3P3, VCC1P8V, VCC1P0V AND VSS 5 - 82575 PCI EXPRESS, JTAG, AUX POWER, LAN DISABLE, MAIN POWER OK AND DEVICE OFF 6 - SERDES FIBER OPTIC OPTION A - SHOWS IMPLEMENTATION FOR BOTH PORT 0 AND 1. 7 - SERDES BACKPLANE OPTION B - SHOWS IMPLEMENTATION FOR BOTH PORT 0 AND 1. REVISION HISTORY 1.0 DOCUMENT RELEASE 1.1 - UPDATE COMMENTS - MOVE TDIS_0 TO PIN B17 (SDP0_2)) - MOVE TDIS_1 TO PIN A13 (SDP1_2 1.2 - CORRECT U1-T23,T24 NET NAMES 2.0 - ADD PU/PD ON NCSI (SHEET2) 1 - TITLE PAGE LAN ACCESS DIVISIONNUE 2111 N.E. 25th AVE24 HILLSBORO, OR 971 8 TITLE 7 82575 REF DESIGN - SERDES/FIBER 6 5 SIZE B CODE DOCUMENT NUMBER 4 324964-002 3 2.0 REV 01/11 DATE 2 0 SHEET 1 B A 8 C SPI EEPROM SPI FLASH 7 6 5 4 FUNCTIONAL BLOCK DIAGRAM ETHERNET NOT SHOWN IN SERDES VERSION 3 82575 LAN CONTROLLER SERDESA PORT SERDESB PORT OPTION A - SERDES LASER APPLICATION FOR BOTH PORTS. OPTION B - SERDES BACKPLANE APPLICATION FOR BOTH PORTS. 2 B A SMBUS/I2C/NCSI JTAG PCI-EXPRESS X4 +3.3V MAIN +3.3V AUX FOR REFERENCE POWER SUPPLY IMPLEMENTATION OPTIONS PLEASE REFER TO THE DESIGN GUIDE. POWER SUPPLY DELIVERY CUSTOMER IS RESPONSIBLE FOR DELIVERING A +3.3V SUPPLY THAT IS DERIVED FROM THE PLATFORM MAIN OR AUX SUPPLY RAILS. THE +1.8V AND +1.0V SUPPLY'S CAN BE DERIVED FROM THE +3.3V SUPPLY UTILIZING EITHER LINEAR OR SWITCHING REGULATOR TECHNOLOGIES. +3.3V LAN (3P3V_LAN) FOR SCHEMATIC +1.8V LAN (1P8V_LAN) FOR SCHEMATIC +1.0V LAN (1P0V_LAN) FOR SCHEMATIC 2 - FUNCTIONAL BLOCK DIAGRAM LAN ACCESS DIVISIONNUE 2111 N.E. 25th AVE24 HILLSBORO, OR 971 8 LEGEND SOLID LINE INDICATES THAT THE CONNECTIONS ARE SHOWN IN REFERENCE SCHEMATIC. DASHED LINE INDICATES THAT THE CONNECTIONS ARE NOT SHOWN IN REFERENCE SCHEMATIC. THESE CONNECTIONS ARE OWNED BY THE SYSTEM DESIGNER. TITLE 7 82575 REF DESIGN - SERDES/FIBER 6 5 SIZE B CODE DOCUMENT NUMBER 4 324964-002 3 2.0 REV 01/11 DATE 2 1 C B A 1 SHEET 1 8 3P3V_LAN 7 6 5 4 3 2 1 PULL UP RESISTOR VALUES SHOULD BE ADJUSTED BY SYSTEM DESIGNER DEPENDING ON SYSTEM ARCHITECTURE. 5% 2 R39 10.0K 1 5% 2 R40 10.0K 1 5% 2 R41 10.0K 1 C B A TOTAL TRACE LENGTH SHOULD BE LESS THAN. 1 INCH. 2 R2 1 1% 1.40K 7 6 7 6 7 6 7 6 6 7 6 7 6 7 6 6 7 6 IN IN IN IN IN IN OUT OUT OUT OUT SRDS0_SIG_DET SRDS1_SIG_DET J234 SRDSI_0_P SRDSI_0_N J2 K234 SRDSO_0_P K2 SRDSO_0_N A9 SRDSI_1_N T24 T23 SRDSI_1_P R234 SRDSO_1_P SRDSO_1_N R2 A10 C53 TRACE LENGTHS SHOULD BE LESS THAN 0.75 INCHES. THESE ARE NOT DIFFERENTIAL SIGNALS. FOR DETAIL PLEASE REFER TO THE Read the full D.

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