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Includes required, recommended, and optional UEFI protocols and elements as well as notes on design strategies and implementation for each protocol.
Includes required, recommended, and optional UEFI protocols and elements as well as notes on design strategies and implementation for each protocol.
Guide: Measures performance of Autodesk* 3ds Max* 2009. The results and procedures give a glimpse of its performance on application software.
Guide: Measures performance of AutoMKV* (x264). The results and procedures give a glimpse of its performance with Media Encoding.
Guide on Intel® processor performance in Microsoft Office Excel* 2007 using Black-Scholes* option pricing model in a Monte Carlo* simulation.
Guide on Intel® processor performance in Microsoft Office Excel 2007* during a heavy number crunch.
A guide measuring performance of the Intel® Processors on Adobe Premiere Pro CS3* patch 3.1.1.
Guide for testing and measuring performance benefits for the Pentium® processor using WinRAR 3.71* archive compression application software.
Software Developers Guide: Intel® Xeon Phi™ coprocessor architecture, power management, RAS features, OS support, APIs, usage models, more.
Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.
Defines core code for implementation of Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.
Updated: Defines the basic components, status code classes, and status code architecture required for Intel® Platform Innovation Framework for EFI.
Presentation: IBM, Intel on enterprise security, trusted computing elements and best practices.
Code and services for data hub in Intel® Platform Innovation Framework for EFI. Hub is a volatile database intended as focus for manageability data.
Defines core code for an implementation of the Firmware File System of the Intel® Platform Innovation Framework for EFI.
Specification, 0.91: core code and services to implement the Driver Execution Environment phase of the Intel® Platform Innovation Framework for EFI.
Hand-Off Block Specification for the Intel® Platform Innovation Framework for EFI defines core code required for implementation.
Specification defines required core code and services for the memory data hub subclass of the Intel® Platform Innovation Framework for EFI.
PCI Host Bridge Resource Allocation Protocol Specification for the Intel® Platform Innovation Framework for EFI defines core code and implementation.
Defines core code for an implementation of the Pre-EFI Initialization phase of the Intel® Platform Innovation Framework for EFI.
Download delle presentazioni su Intel® Unified Extensible Firmware Interface (UEFI) dall'edizione 2010 di Intel Developer Forum (IDF).
Defines core code for an implementation of the processor data hub subclass of the Intel® Platform Innovation Framework for EFI.
Defines the recovery architecture, core code, and services required for the implementation of the in the Intel® Platform Innovation Framework for EFI.
Defines the core code and services required of the S3 Resume Boot Path for the Intel® Platform Innovation Framework for EFI.
Defines the core code, services, and design required in the SMBus Host Controller Protocol for the Intel® Platform Innovation Framework for EFI.